General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing
نویسندگان
چکیده
منابع مشابه
Soft Error-Aware Power Optimization Using Gate Sizing
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application specific designs. Gate sizing has been shown to be one of the most effective methods for power (and area) reduction in CMOS digital circuits. Recently, as the feature size of logic gates (and transistors) is becoming smaller and smaller, the effect of soft error rates caused by sin...
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We evaluate the effectiveness of statistical gate sizing to minimize circuit power. We develop reliable posynomial models for delay and power that are accurate to within 5-10% of 130nm library data. We formulate statistical sizing as a geometric program, accounting for randomness in gate delays. For various ISCAS-85 circuits, statistical sizing at a 99.8% target yield provides 25% power reducti...
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Gate sizing has a significant impact on the delay, power dissipation, and area of the final circuit. It consists of choosing for each node of a mapped circuit a gate implementation in the library so that a cost function is optimized under some constraints. For instance, one wants to minimize the power consumption and/or the area of a circuit under some user-defined delay constraints, or to obta...
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| With the growing scale of integration and the increased use of battery operated devices the power dissipation of CMOS circuits becomes an important factor in the design process. Power dissipation in CMOS-gates depends on the capacity switched and the transition density. Gate sizing is used to scale gates and their internal capacities. Smaller gates mean smaller capacities and therefore less p...
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In this paper we present a new transistor sizing methodology called Free Power Recovery (FPR) for low power circuit design. The objective of this methodology is to minimize the total power of a circuit by accounting for node switching activities and leakage duty cycles (LDC). The methodology has been incorporated into the EinsTuner circuit tuning tool. EinsTuner automates the tuning process usi...
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ژورنال
عنوان ژورنال: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
سال: 2008
ISSN: 0278-0070
DOI: 10.1109/tcad.2008.2003268